The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In a conventional integrated circuit, a substrate is typically covered with a number of layers of conductive or other material, which are patterned to form a plurality of signal lines that determine the circuit layout. Interconnections between the signal lines may be formed, e.g., by vias or contacts, that run between or through the various layers. The term “contact” will be used throughout this disclosure as a generic term encompassing any electrical interconnections between signal lines, specifically including, but not limited to, contacts between metal and poly lines and vias between two metal lines. In some memory arrays, these signal lines run perpendicular to each other.
FIGS. 1A and 1B illustrate a prior art memory array 40 having parallel signal lines. As shown in FIG. 1A, the memory array 40 includes a substrate 45 having a plurality of diffusion lines 46-1 to 46-4. A plurality of poly lines 47-1 to 47-3 and metal lines 48-1 to 48-4 are layered on top of substrate 45, and are parallel to diffusion lines 46. Referring to FIG. 1B, memory array 40 is constructed by layering poly lines 47 over substrate 45, including diffusion lines 46, and then layering the metal lines 48 to reside on top of the poly layer. Each of these layers is respectively separated from one another by an insulating barrier layer 44-1 to 44-3. Metal lines 48-1 to 48-4 are connected to diffusion lines 46-1 to 46-4 by means of contacts 49. These contacts 49 must run from the metal line layer to the diffusion layer and, thus, travel through the layer that contains poly lines 47-1 to 47-3 (see FIG. 1B). In this configuration, the pitch of the signal lines cannot be at a minimum feature because of the possibility that contacts 49 will “touch” or contact with poly lines 47, as described below.
In FIG. 1B, the proximity between contacts 49 and poly lines 47 at locations 490-1 to 490-6 leads to an unacceptable risk of short circuit. If the width of the signal lines is at minimum feature, the contacts 49 may be immediately adjacent to poly lines 47. Thus, a circuit designer may choose to make the width of the signal lines wider than the pitch of contacts 49. In the prior art integrated circuit layout of FIG. 1B, an integrated circuit manufacturer may provide extra spacing (or a buffer) between poly lines 47 and contacts 49 at locations 490-1 to 490-6 to reduce the possibility of interconnection between poly lines 47 and contacts 49. The addition of these buffer areas requires the utilization of more surface area on the substrate 45. In this manner, a circuit designer may reduce the potential for contact/poly lines interconnection, but only at the cost of utilizing a larger surface area on the substrate 45.